Teresa Cervero García
Leading Research Engineer, Barcelona Supercomputing Center (BSC)
PhD. in Telecommunication Engineering focused on hardware design with experience on HDL languages and FPGA devices.
Hardware coordinator of the European MEEP (MareNostrum Experimental Exascale Platform) project.
Research interests in:
- Dynamic reconfigurable FPGA-based systems,
- High Performance Computing accelerators
- Scalable architectures
- Parallel Computing
- Embedded Systems